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| pc133 clock generator for sis630/pentium ? iii & sis540/socket7 applications cypress semiconductor corporation 3901 north first st. document #: 38-07035 rev. *a 12/18/2002 san jose, ca 95134. tel: 408-943-2600 page 1 of 18 http://www.cypress.com a pproved produc t c9630 product features ? supports pentium iii, k6, and socket 7 cpu?s ? designed to sis630 & sis540 chipset requirements ? 3 copies of cpu clock (cpu[0:2] ) ? 14 copies of sdram clock (sdram[0:13] ? 7 copies of pci clock ? 2 ref(0:1) clock outputs ? 1 usb clock (non ssc), 48mhz ? 1 programmable sio (non ssc), 24/48mhz ? 133 mhz sdram support ? cypress spread spectrum for best emi reduction ? smbus support with read back capabilities. ? dial-a-frequency? feature ? 48 pin ssop package. block diagram fig.1 frequency table (mhz) fs3 fs2 fs1 fs0 cpu sdram pciclk 0 0 0 0 66.6 100.0 33.3 0 0 0 1 100.0 100.0 33.3 0 0 1 0 150.0 100.0 37.5 0 0 1 1 133.3 100.0 33.3 0 1 0 0 66.8 133.6 33.4 0 1 0 1 100.0 133.3 33.3 0 1 1 0 100.0 150.0 37.5 0 1 1 1 133.3 133.3 33.3 1 0 0 0 66.9 66.9 33.4 1 0 0 1 97.2 97.2 32.4 1 0 1 0 70.0 105.0 35.0 1 0 1 1 95.0 95.0 31.6 1 1 0 0 95.0 126.7 31.6 1 1 0 1 112.0 112.0 37.3 1 1 1 0 97.0 129.3 32.4 1 1 1 1 96.0 96.0 32.0 table 1 note: *programmable to 48 mhz via smbus pin configuration fig.2 vdd vdd vddcpu vdd vdd vdd vdd vdd vdd xin xout ref1 ref0/s3 cpu(0:2) sdram(0:13) pci(2:6) pci0/s1 pci1/s2 48mhz/s0 24_48mhz sdat a sclk pll1 rin s1 s0 sdata sclk cpu sdram pci s3 s2 pll2 rin 48 i2c-clk i2c-data 24 or 48 1 1 30pf 300k 30pf 3 14 5 1 1 1 1 vdd s3 / ref0 vss xin xou t vdd s1/ pci0 s2 / pci1 pci2 vss pci3 pci4 pci5 pci6 vdd vss sdram0 sdram1 vdd sdram2 sdram3 vss sdat a scl k ref1 vdd c cpu0 cpu1 vss cpu2 vd d sdram13 sdram12 vss sdram11 sdram10 vd d sdram9 sdram8 vss sdram7 sdram6 vd d sdram5 sdram4 vd d s0 / 48mhz 24_48mhz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
pc133 clock generator for sis630/pentium ? iii & sis540/socket7 applications cypress semiconductor corporation 3901 north first st. document #: 38-07035 rev. *a 12/18/2002 san jose, ca 95134. tel: 408-943-2600 page 2 of 18 http://www.cypress.com a pproved produc t c9630 pin description pin no. pin name pwr i/o description 2 s3/ ref0 vdd i/o 3.3v 14.318 mhz clock output. this is a power on bi-directional pin. during power up, this pin is an input ?s3? for setting the cpu frequency (see table1, page 1) (see app note, page 5). when the power reaches the rail, this pin becomes a buffered output of the signal applied at xin (typically 14.318 mhz). 48 ref1 vdd o this pin is a buffered output of the signal applied at xin (typically 14.318) 4 xin vdd i 14.318mhz crystal input 5 xout vdd o 14.318mhz crystal output 7 s1/ pci0* vdd i/o this is a power on bi-directional pin. during power up, this pin is an input ?s1? for setting the cpu frequency (see table1, page 1) (see app not, page 5). when the power reaches the rail, this pin becomes a pci0 clock output. 8 s2/ pci1* vdd i/o this is a power on bi-directional pin. during power up, this pin is an input ?s2? for setting the cpu frequency (see table1, page 1) (see app not, page 5). when the power reaches the rail, this pin becomes a pci1 clock output. 9,11,12,13, 14 pci(2:6) vdd o 3.3v pci clock outputs. 25 24/48mhz vdd o this pin is programmable to 24mhz or 48 mhz clock output through smbus. it defaults to 24mhz at power up. 26 s0 / 48mhz* vdd i/o this is a power on bi-directional pin. during power up, this pin is an input ?s0? for setting the cpu frequency (see table1, page 1) (see app note, page 5). when the power reaches the rail, this pin becomes a 48mhz clock output. this clock conforms to the usb spec. of +167ppm. 28 sdata vdd i smbus compatible sdata input. has an internal pull-up (>100k ? ) 29 sclk vdd i smbus compatible sclk input. has an internal pull-up (>100k ? ) 17,18,20,21, 28,29,31,32, 34,35,37,38, 40,41 sdram(0:13) vdd o 3.3v sdram clock outputs. see table1, p.1 for frequency selection. 43,45,46 cpu(0:2) vddc o 2.5v or 3.3v host bus clock outputs. see table 1, page 1 for frequency selection. 1,6,15,19, 27, 30,36,42 vdd - 3.3v common power supply 47 vddc - 2.5v or 3.3v power supply?s for cpu (0:2) clock outputs. 3,10,16,22, 33,39,44 vss - common ground pin. a bypass capacitor (0.1 f) should be placed as close as possible to each positive power pin. if these bypass capacitors are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces. *note: these pins have pulldown resistors, typical value 250 ? . pc133 clock generator for sis630/pentium ? iii & sis540/socket7 applications cypress semiconductor corporation 3901 north first st. document #: 38-07035 rev. *a 12/18/2002 san jose, ca 95134. tel: 408-943-2600 page 3 of 18 http://www.cypress.com a pproved produc t c9630 device clock phase relationships fig.3 frequency smooth switching groups group s(4:0) 1 00001, 00010, 00111, 01101, 10001, 10010, 10111, 11010, 11011, 11100, 11101, 11110, 11111 2 00000, 00011, 00110, 01010, 10000, 10101 3 00100, 00101, 01000, 01001, 01011, 01100, 01110, 01111, 10011, 10100, 10110, 11000, 11001 table 2 table 2 above describes 3 different groups of frequencies. within the same group, frequency may be switched through smbus byte 0 without causing any glitching or clock discontinuity at the cpu(0:2) outputs, therefore allowing frequency smooth switching of the clock. switching frequency from one group to another is permitted but will cause the cpu(0:2) clocks to jump immediately to the next frequency. (non smooth switching.). internal vco internal vco internal vco sdra m to cpu or cpu to sdram applicable to the follow ing selection: s(4:0) = 00100 tskew 3 condition 3: cpu frequency = 1.3 x sdram frequency or sdram frequency = 1.3 x cpu frequency applicable to the follow ing selections: s(4:0) = 00000, 00010, 00110, 01010, 10000, 10010, 10101 condition 2: cpu frequency = 1.5 x sdram frequency or sdram frequency = 1.5 x cpu frequency condition 1: cpu frequency = sdram frequency tskew 3 applicable to the follow ing selections: s(4:0) = 00011, 00101, 01100, 01110, 10011, 10100, 10110, 11000, 11001 tskew 3 applicable to the follow ing selections: s(4:0) = 00001, 00111, 01000, 01001, 01011, 01101, 01111, 10001, 10111,11010, 11011, 1 1100, 11101, 11110, 11111 condition 4: sdram frequency = 2 x cpu frequency tskew 3 or cpu sdra m to cpu t o sdra m or cpu sdra m to cpu t o sdra m sdra m cpu internal vco pc133 clock generator for sis630/pentium ? iii & sis540/socket7 applications cypress semiconductor corporation 3901 north first st. document #: 38-07035 rev. *a 12/18/2002 san jose, ca 95134. tel: 408-943-2600 page 4 of 18 http://www.cypress.com a pproved produc t c9630 power on bi-directional pins power up condition: pins 2,7,8,and 26 are power up bi-directional pins used for selecting the host frequency in page 1, table 1. during power-up of the device, these pins are in input mode (see fig 4, below), therefore; they are considered input select pins internal to the ic. after a settling time, the selection data is latch into the internal control register and these pins becom e a clock outputs. - hi-z input toggle outputs power supply ramp select data is latched into register, then pin becomease ref clock output signal. ref0 / s3 pci0 / s1 pci1 / s2 48mhz / s0 vdd rail strapping resistor options: the power up bi-directional pins have a large value pull- down each (250k ?) , therefore, a selection ?0? is the default. if the system uses a slow power supply (over 5ms settling time), then it is recommended to use an external pull-down (rdn) in order to insure a low selection. in this case, the designer may choose one of two configurations, see fig.5a and b. fig. 5a represents an additional pull down resistor rdn = 50k ? connected from the pin to the ground plane, which allows a faster pull to a low level. if a selection ?1? is desired, then a jumper is placed on jp1 to a rup = 10k ? resistor as implemented as shown in fig.5a. please note the selection resistors (rup and rdn ) are placed before the damping resistor (rd) close to the pin. fig. 5b represent a single resistor 10k ? connected to a 3-way jumper, jp2. when a ?1? selection is desired, a jumper is placed between leads1 and 3. when a ?0? selection is desired, a jumper is placed between leads 3 and 2. fig.4 fig.5a fi g .5b 123 load load vdd vdd imic9630 bidirectional 10k 50k rd jp1 imic9630 bidirectional rd 10k jp2 pc133 clock generator for sis630/pentium ? iii & sis540/socket7 applications cypress semiconductor corporation 3901 north first st. document #: 38-07035 rev. *a 12/18/2002 san jose, ca 95134. tel: 408-943-2600 page 5 of 18 http://www.cypress.com a pproved produc t c9630 2-wire smbus control interface the 2-wire control interface implements a read/write slave only interface according to smbus specification (ic12, 1996). the device can be read back by using standard smbus command bytes. sub addressing is not supported, thus all preceding bytes must be sent in order to change one of the control bytes. the 2-wire control interface allows each clock output to be individually enabled or disabled. 100 kbits/second (standard mode) data transfer is supported. during normal data transfer, the sdata signal only changes when the sclk signal is low, and is stable when sclk is high. there are two exceptions to this. a high to low transition on sdata while sclk is high is used to indicate the start of a data transfer cycle. a low to high transition on sdata while sclk is high indicates the end of a data transfer cycle. data is always sent as complete 8-bit bytes, after which an acknowledge is generated. the first byte of a transfer cycle is a 7-bit address with a read/write bit (r/w#) as the lsb. r/w# = 1 in read mode. r/w# = 0 in write mode. a maximum of 10 bytes of data may be written/read data is transferred msb first at a max rate of 100kbits/s.the device will not respond to any other control interface conditions. in the write mode (see fig6a, p.9), the clock gen. acknowledges address byte, d2, then receives two additional bytes: 1) ? command code ? byte, and 2) ? byte count ? byte. must be programmed to ff for correct operation. although the data (bits) in these two bytes are considered ?don?t care?; they must be sent and will be acknowledged. subsequently, the below-described sequence (byte 0, byte 1, byte2,) will be valid and acknowledged. in the read mode (see fig6b, p.9), the clock gen. acknowledges address d3, and immediately transmits data starting with byte count, then byte 0, 1, 2, ... after each transmitted byte, this device waits for an acknowledge before transmitting the next byte. serial control registers note: power up conditions for each bit are listed in the ?@pup? column. byte 0: frequency, function select register bit @pup pin# description, see page 8 for sscg description. 7 0 n/a s4 (for frequency table 3, selection by software via smbus), selection valid if bit3 = 1 6 0 n/a s2 (for frequency table 3, selection by software via smbus), selection valid if bit3 = 1 5 0 n/a s1 (for frequency table 3, selection by software via smbus), selection valid if bit3 = 1 4 0 n/a s0 (for frequency table 3, selection by software via smbus), selection valid if bit3 = 1 3 0 n/a 0 = frequency selected by hardware, pins 2,7,8,26 1 = frequency selection via smbus byte0. bits 4,5,6,2,7 2 0 n/a s3 (for frequency table 3, selection by software via smbus), selection valid if bit3 = 1 1 0 n/a 0 = spread spectrum disabled 1 = spread spectrum enabled 0 0 n/a 0 = running 1 = test mode. pc133 clock generator for sis630/pentium ? iii & sis540/socket7 applications cypress semiconductor corporation 3901 north first st. document #: 38-07035 rev. *a 12/18/2002 san jose, ca 95134. tel: 408-943-2600 page 6 of 18 http://www.cypress.com a pproved produc t c9630 serial configuration command bitmap byte0: functionality and frequency select register (default = 0) s4 s3 s2 s1 s0 description bit7 bit2 bit6 bit5 bit4 cpu sdram pci spread spectrum, mbs0 = mbs1 = 1, ssts = 1 0 0 0 0 0 66.6 100.0 33.3 0 to ?0.5% 0 0 0 0 1 100.0 100.0 33.3 0 to ?0.5% 0 0 0 1 0 150.0 100.0 37.5 +/- 0.25% 0 0 0 1 1 133.3 100.0 33.3 0 to ?0.5% 0 0 1 0 0 66.8 133.6 33.4 0 to ?0.5% 0 0 1 0 1 100.0 133.3 33.3 0 to ?0.5% 0 0 1 1 0 100.0 150.0 37.5 +/- 0.25% 0 0 1 1 1 133.3 133.3 33.3 0 to ?0.5% 0 1 0 0 0 66.8 66.8 33.4 +/- 0.25% 0 1 0 0 1 97.0 97.0 32.3 0 to ?0.5% 0 1 0 1 0 70.0 105.0 35.0 +/- 0.25% 0 1 0 1 1 95.0 95.0 31.7 +/- 0.25% 0 1 1 0 0 95.0 126.7 31.7 +/- 0.25% 0 1 1 0 1 112.0 112.0 37.3 +/- 0.25% 0 1 1 1 0 97.0 129.3 32.3 0 to ?0.5% 0 1 1 1 1 96.2 96.2 32.1 0 to ?0.5% 1 0 0 0 0 66.8 100.2 33.4 +/- 0.25% 1 0 0 0 1 100.2 100.2 33.4 +/- 0.25% 1 0 0 1 0 166.0 110.7 33.3 +/- 0.25% 1 0 0 1 1 100.2 133.6 33.4 +/- 0.25% 1 0 1 0 0 75.0 100.0 37.5 +/- 0.25% 1 0 1 0 1 83.3 125.0 31.3 +/- 0.25% 1 0 1 1 0 105.0 140.0 35.0 +/- 0.25% 1 0 1 1 1 133.6 133.6 33.4 +/- 0.25% 1 1 0 0 0 110.3 147.0 36.8 +/- 0.25% 1 1 0 0 1 115.0 153.3 38.3 +/- 0.25% 1 1 0 1 0 120.0 120.0 30.0 +/- 0.25% 1 1 0 1 1 138.0 138.0 34.5 +/- 0.25% 1 1 1 0 0 140.0 140.0 35.0 +/- 0.25% 1 1 1 0 1 145.0 145.0 36.3 +/- 0.25% 1 1 1 1 0 147.5 147.5 29.5 +/- 0.25% 1 1 1 1 1 160.0 160.0 32 +/- 0.25% table 3. test function table: applicable only when bit0=1 in byte0. cpu (0:2) pci (0:6) sdram (0:13) ref(0,1) 48mhz 24_48mhz = xin / 3 = xin / 6 = xin / 2 = xin = xin = xin / 2 test clock should be applied at xin pin. pc133 clock generator for sis630/pentium ? iii & sis540/socket7 applications cypress semiconductor corporation 3901 north first st. document #: 38-07035 rev. *a 12/18/2002 san jose, ca 95134. tel: 408-943-2600 page 7 of 18 http://www.cypress.com a pproved produc t c9630 serial control registers (cont.) byte 1: cpu clock register (1 = enable, 0 = stopped) bit @pup pin# description 7 1 - selects frequency at pin 25 1 = selects 24mhz (default) 0 = selects 48mhz 6 1 - ssts, see table 4, p 11 5 1 - reserved for imi test^ 4 1 - reserved for imi test^ 3 1 43 cpu2 enable/stopped 2 1 45 cpu1 enable/stopped 1 1 46 cpu0 enable/stopped 0 1 - reserved for imi test^ byte 2: pci clock register (1 = enable, 0 = stopped) bit @pup pin# description 71 - reserved 6 1 14 pci6 enable/stopped 5 1 13 pci5 enable/stopped 4 1 12 pci4 enable/stopped 3 1 11 pci3 enable/stopped 2 1 9 pci2 enable/stopped 1 1 8 pci1 enable/stopped 0 1 7 pci0 enable/stopped byte 3: sdram clock register (1 = enable, 0 = stopped) bit @pup pin# description 7 1 32 sdram7 enable/stopped 6 1 31 sdram6 enable/stopped 5 1 29 sdram5 enable/stopped 4 1 28 sdram4 enable/stopped 3 1 21 sdram3 enable/stopped 2 1 20 sdram2 enable/stopped 1 1 18 sdram1 enable/stopped 0 1 17 sdram0 enable/stopped byte 4: additional sdram clock register (1=enable, 0=stopped) bit @pup pin# description 7 1 25 24_48mhz enable/stopped 6 1 26 48 mhz enable/stopped 5 1 41 sdram13 enable/stopped 4 1 40 sdram12 enable/stopped 3 1 38 sdram11 enable/stopped 2 1 37 sdram10 enable/stopped 1 1 35 sdram9 enable/stopped 0 1 34 sdram8 enable/stopped byte 5: peripheral control (1 = enable, 0 = stopped) bit @pup pin# description 71 - mbs1 , see table 4, p. 11 for spread spectrum 61 - mbs0 , see table 4, p.11 for spread spectrum 5 1 - s3# * 4 1 - s2# * 3 1 - s1# * 2 1 - s0# * 1 1 48 ref1 enable/stopped 0 1 2 ref0 enable/stopped * inverted read back of hardware settings. byte 6: reserved register (1 = enable, 0 = stopped) bit @pup pin# description 7 0 - reserved for imi test^ 60 - 50 - 4 0 - reserved for imi test^ 3 0 - reserved for imi test 2 1 - reserved for imi test 10 -n9, msb 00 -n8 byte 7: dial-a-frequency? n register (1 = enable, 0 = stopped) bit @pup pin# description 70 -n7 60 -n6 50 -n5 40 -n4 30 -n3 20 -n2 10 -n1 0 0 - n0, lsb byte 8: dial-a-frequency? r register (1 = enable, 0 = stopped) bit @pup pin# description 70 -r6, msb 60 -r5 50 -r4 40 -r3 30 -r2 20 -r1 1 0 - r0, lsb 0 0 - 1 = enable smbus n and r pc133 clock generator for sis630/pentium ? iii & sis540/socket7 applications cypress semiconductor corporation 3901 north first st. document #: 38-07035 rev. *a 12/18/2002 san jose, ca 95134. tel: 408-943-2600 page 8 of 18 http://www.cypress.com a pproved produc t c9630 dial-a-frequency ? feature smbus dial-a-frequency ? feature is available in this device via byte7, and byte 8 these bytes allow the user to enter the n and r values that will allow them to program any cpu frequency desired following the formula: where n and r values are programmed in binary into byte 7 for n and byte 8 for r. see table below for min and max allowed values. rmin nmax n 42 44 87 43 45 90 44 46 92 45 47 94 46 48 96 47 49 98 48 50 100 49 51 102 50 52 104 51 53 107 p is a large value pll constant that depends on the last frequency selection achieved through the hardware selectors (s3, s2, s1, s0) or through the software selectors (byte0 , bits 7,6,5,4,2). p value may be determined from the following table: s(4:0) p 00001, 00010, 00111, 01101, 10001, 10010, 10111, 11010, 11011, 11100, 11101, 11110, 11111 96016000 00000, 00011, 00110, 01010, 10000, 10101 64010667 00100, 00101, 01000, 01001, 01011, 01100, 01110, 01111, 10011, 10100, 10110, 11000, 11001 48008000 therefore, if a 145mhz (use 145x10 6 )value is desired, then we should apply 145 into equation 1, and start by choosing r to be 47 (assume the last frequency selection has the value p = 96016000): 145x10 6 = 96016000 x n => n = 70.97775371 47 r n p fcpu = pc133 clock generator for sis630/pentium ? iii & sis540/socket7 applications cypress semiconductor corporation 3901 north first st. document #: 38-07035 rev. *a 12/18/2002 san jose, ca 95134. tel: 408-943-2600 page 9 of 18 http://www.cypress.com a pproved produc t c9630 dial-a-frequency ? feature (cont.) since this n number must be entered in binary, it can only be an integer, so it must be rounded up or down. here we can rounded it up to 71, which will give us an exact cpu frequency of: fcpu = 96016000 x n = 145.045 mhz (accuracy + 310 ppm) 47 if the above frequency is not accurate enough, then you must choose another r value and start from the beginning. for example choose r = 49 and this will yield an n = 73.99808365, which is rounded to 74. if the 74 is applied in the formula 1, then fcpu = 145.0038 mhz (accuracy + 26 ppm). other r values within the above limits may also be evaluated. smbus communication waveform start imi device master device stop condition start condition imi device master device stop condition 1 8 a ck msb 00 0 sdata 0 1 lsb command byte 1 sclk 1 byte n 88 8 byte 0 byte count a ck a ck a ck a ck (don't care) (don't care) (valid) (valid) fig.6a (write) (valid) sdata 1 0 (valid) 0 11 8 byte n (valid) byte count sclk lsb no ack 8 a ck a ck 8 0 byte1 1 a ck a ck msb 8 1 (valid) byte 0 fig.6b (read) pc133 clock generator for sis630/pentium ? iii & sis540/socket7 applications cypress semiconductor corporation 3901 north first st. document #: 38-07035 rev. *a 12/18/2002 san jose, ca 95134. tel: 408-943-2600 page 10 of 18 http://www.cypress.com a pproved produc t c9630 smbus test circuitry fig.7 note: buffer is 7407 with vcc @ 5.0 v spread spectrum clock generation (sscg) spread spectrum is a modulation technique applied here for maximum efficiency in minimizing electro-magnetic interference radiation generated from repetitive digital signals mainly clocks. a clock accumulates em energy at the center frequency it is generating. spread spectrum distributes this energy over a small frequency bandwidth therefore spreading the same amount of energy over a spectrum. this technique is achieved by modulating the clock down from (fig.8a) or around the center (fig.8b) of its resting frequency by a certain percentage (which also determines the energy distribution bandwidth). in this device, spread spectrum is enabled by setting i2c byte0, bit1 = 1. the default of the device at power up keeps the spread spectrum disabled, it is therefore, important to have i2c accessibility to turn-on the spread spectrum function. once the spread spectrum is enabled, the spread bandwidth option is selected by mbs(0:1) in i2c byte 5, bit6 and bit 7, and ssts byte1, bit6 following table 4 below. in down spread mode the center frequency is shifted down from its rested (non-spread) value by ? of the total spread %. (eg.: assuming the center frequency is 100mhz in non-spread mode; when down spread of ?0.5% is enabled, the center frequency shifts to 99.75mhz.). 2.2 k device under test sdata datain sclk dataout clock + 5v + 5v + 5v 2.2 k 2.2 k pc133 clock generator for sis630/pentium ? iii & sis540/socket7 applications cypress semiconductor corporation 3901 north first st. document #: 38-07035 rev. *a 12/18/2002 san jose, ca 95134. tel: 408-943-2600 page 11 of 18 http://www.cypress.com a pproved produc t c9630 spread spectrum clock generation (sscg) (cont.) in center spread mode, the center frequency remains the same as in the non-spread mode. down spread center spread fig.8a fig.8b spread spectrum selection table ssts mbs 1 mbs 0 spread% 00 0 - 0.5 0 0 1 +/- 0.125 0 1 0 +/- 0.5 0 1 1 +/- 0.25 10 0 -0.5 1 0 1 +/- 0.125 1 1 0 +/- 0.5 1 1 1 see table 3, (default) table 4 maximum ratings 1 1 multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing is not required. maximum input voltage relative to vss: vss - 0.3v maximum input voltage relative to vdd: vdd + 0.3v storage temperature: -65oc to + 150oc operating temperature: 0oc to +70oc maximum esd protection 2kv maximum power supply: 5.5v this device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, vin and vout should be constrained to the range: vss<(vin or vout) pc133 clock generator for sis630/pentium ? iii & sis540/socket7 applications cypress semiconductor corporation 3901 north first st. document #: 38-07035 rev. *a 12/18/2002 san jose, ca 95134. tel: 408-943-2600 page 13 of 18 http://www.cypress.com a pproved produc t c9630 ac parameters 133 mhz host 100 mhz host symbol parameter min max min max units notes tperiod cpu(0:2) period 7.45 8.0 9.98 10.5 ns 5, 6, 8 thigh cpu(0:2) high time 1.87 - 3.0 - ns 6,10 tlow cpu(0:2) low time 1.67 - 2.8 - ns 6, 11 tr / tf cpu(0:2) rise and fall times 0.4 1.9 0.4 2.1 ns 6, 7 tskew0 any cpu to any cpu skew time - 175 - 175 ps 6, 8, 9 tccj cpu(0:2) cycle to cycle jitter - 250 - 250 ps 6,8,9,14 tperiod sdram[0:13] period 7.46 8.0 9.89 10.5 ns 5, 6, 8 thigh sdram[0:13] high time 1.87 - 3.0 - ns 6,10 tlow sdram[0:13] low time 1.67 - 2.63 - ns 6, 11 tr / tf sdram[0:13] rise and fall times 0.4 1.69 0.4 1.88 ns 6, 7 tskew1 any sdram to any sdram - 500 - 500 ps 6, 8, 9 tccj sdram[0:13] cycle to cycle jitter - 250 - 250 ps 6,8,9,14 tperiod pci(0:6) period 29.93 - 29.94 - ns 5, 6, 8 thigh pci(0:6) period 12.0 - 12.0 - ns 6,10 tlow pci(0:6) low time 12.0 - 12.0 - ns 6, 11 tr / tf pci(0:6) rise and fall times 0.5 2.9 0.5 2.9 ns 6, 7 tskew2 (any pci clock) to (any pci clock) - 500 - 500 ps 6, 8, 9 tccj pci(0:6) cycle to cycle jitter - 500 - 500 ps 6, 8, 9 tperiod 48mhz period ( conforms to +167ppm max) 20.8212 20.8333 20.8299 20.8442 ns 5, 6, 8 tr / tf 48mhz rise and fall times 1.0 4.0 1.0 4.0 ns 6, 7 tccj 48mhz cycle to cycle jitter - 500 - 500 ps 6, 8, 9 tperiod 24mhz period 41.6087 41.6666 41.6026 41.6666 ns 5, 6, 8 tr / tf 24mhz rise and fall times 1.0 4.0 1.0 4.0 ns 6, 7 tccj 24 mhz cycle to cycle jitter - 500 - 500 ps 6, 8, 9 tperiod ref(0:1) period 69.8167 71.0 69.8017 71.0 ns 5, 6, 8 tr / tf ref0 rise and fall times 1.0 4.0 1.0 4.0 ns 6, 7 tr / tf ref1 rise and fall times 1.0 4.0 1.0 4.0 ns 6, 7 tccj ref(0:1) cycle to cycle jitter - 1000 - 1000 ps 6, 8 tpzl, tpzh output enable delay (all outputs) 1.0 10.0 1.0 10.0 ns 13 tplz, tphz output disable delay (all outputs) 1.0 10.0 1.0 10.0 ns 13 tstable all clock stabilization from power-up 3 3 ms 12 tskew3 cpu to sdram (see fig.3, p.3) 0 340 0 354 ps 5, 6, 8 pc133 clock generator for sis630/pentium ? iii & sis540/socket7 applications cypress semiconductor corporation 3901 north first st. document #: 38-07035 rev. *a 12/18/2002 san jose, ca 95134. tel: 408-943-2600 page 14 of 18 http://www.cypress.com a pproved produc t c9630 note 5: this parameter is measured as an average over 1us duration, with a crystal center frequency of 14.31818mhz note 6: all outputs loaded as per table 5. note 7: probes are placed on the pins, and measurements are acquired between 0.4v and 2.4v for 3.3v signals and between 0.4v and 2.0v for 2.5v signals (see fig.9a and fig.9b) note 8: probes are placed on the pins, and measurements are acquired at 1.5v for 3.3v signals and at 1.25v for 2.5v signals. (see figs.9a & 9b) note 9: this measurement is applicable with spread on or spread off. note 10: probes are placed on the pins, and measurements are acquired at 2.4v for 3.3v signals and at 2.0v for 2.5v signals, (see figs. 9a & 9b) note 11: probes are placed on the pins, and measurements are acquired at 0.4v. note 12: the time specified is measured from when all vdd?s reach their respective supply rail (3.3v and 2.5v) till the frequency output is stable and operating within the specifications note 13: measured from when both sel1 and sel0 are low note 14: guaranteed by design in system application (cpu frequency = sdram frequency) test and measurement condition fig. 9a fig. 9b - - 2.4v 0.4v 3.3v 0v t r tf 1.5v 3.3v signals tdc 0.4v 2.0v 1.25v 2.5v 0v 2.5v signals tdc t r tf probe output under test load cap - - pc133 clock generator for sis630/pentium ? iii & sis540/socket7 applications cypress semiconductor corporation 3901 north first st. document #: 38-07035 rev. *a 12/18/2002 san jose, ca 95134. tel: 408-943-2600 page 15 of 18 http://www.cypress.com a pproved produc t c9630 output buffer characteristics cpu(0:2), vddc = 2.5v +/-5% characteristic symbol min typ max units conditions, vddc = 2.5v pull-up current ioh 1 -14.8 -25 -35.5 ma vout =vddc - 0.5v pull-up current ioh 2 -28.4 -58 -79.5 ma vout = 1.25 v pull-down current iol 1 11.7 20 29.3 ma vout = 0.4 v pull-down current iol 2 27 56 67.6 ma vout = 1.2 v dynamic output impedance z0 13.5 45 ? cpu(0:2), vddc = 3.3v +/-5% characteristic symbol min typ max units conditions, vddc= 3.3v pull-up current ioh 1 17 28 40 ma vout =vddc - 0.5v pull-up current ioh 2 53 100 138 ma vout = 1.25 v pull-down current iol 1 13 22 32 ma vout = 0.4 v pull-down current iol 2 35 68 83 ma vout = 1.2 v dynamic output impedance z0 10.4 37 ? pci(0:6), and ref0 characteristic symbol min typ max units conditions pull-up current ioh 1 -33 -58 -194 ma vout =vdd - 1.0 v pull-up current ioh 2 -30 -54 -184 ma vout = 1. 5 v pull-down current iol 1 9.4 18 38 ma vout = 0.4 v pull-down current iol 2 28 55 148 ma vout = 1.5 v dynamic output impedance z0 12 55 ? 24mhz, 48mhz, and ref1 characteristic symbol min typ max units conditions pull-up current ioh 1 -29 -46 -99 ma vout =vdd - 1.0 v pull-up current ioh 2 -27 -43 -92 ma vout = 1. 5 v pull-down current iol 1 9 13 27 ma vout = 0.4 v pull-down current iol 2 26 39 79 ma vout = 1.5 v dynamic output impedance z0 20 60 ? buffer characteristics for sdram(0:13) characteristic symbol min typ max units conditions pull-up current ioh 1 -72 -116 -198 ma vout =vdd - 1. 0 v pull-up current ioh 2 -68 -110 -188 ma vout = 1. 4 v pull-down current iol 1 23 34 53 ma vout = 0.4 v pull-down current iol 1 64 98 159 ma vout = 1.5 v dynamic output impedance z0 10 24 ? vdd=3.3v 5%, ta=0 to 70oc pc133 clock generator for sis630/pentium ? iii & sis540/socket7 applications cypress semiconductor corporation 3901 north first st. document #: 38-07035 rev. *a 12/18/2002 san jose, ca 95134. tel: 408-943-2600 page 16 of 18 http://www.cypress.com a pproved produc t c9630 suggested oscillator crystal parameters characteristic symbol min typ max units conditions frequency f o 12.00 14.31818 16.00 mhz tolerance t c - - +/-100 ppm note 1 t s - - +/- 100 ppm stability (t a -10 to +60c) note 1 t a - - 5 ppm aging (first year @ 25c) note 1 operating mode - - - - parallel resonant, note 1 load capacitance c xtal - 16 - pf the crystal?s rated load. note 1 effective series resistance (esr) r esr - 40 - ohms note 2 note1: for best performance and accurate frequencies from this device, it is recommended but not mandatory that the chosen crystal meets or exceeds these specifications note 2: larger values may cause this device to exhibit oscillator startup problems to obtain the maximum accuracy, the total circuit loading capacitance should be equal to c xtal . this loading capacitance is the effective capacitance across the crystal pins and includes the clock generating device pin capacitance (c ftg ), any circuit traces (c pcb ), and any onboard discrete load capacitors (c disc ). the following formula and schematic may be used to understand and calculate either the loading specification of a crystal for a design or the additional discrete load capacitance that must be used to provide the correct load to a known load rated crystal. c l = (c xinpcb + c xinftg + c xindisc ) x (c xoutpcb + c xoutftg + c xoutdisc ) (c xinpcb + c xinftg + c xindisc ) + (c xoutpcb + c xoutftg + c outdisc ) where: c xtal = the load rating of the crystal c xoutftg = the clock generators xin pin effective device internal capacitance to ground c xoutftg = the clock generators xout pin effective device internal capacitance to ground c xinpcb = the effective capacitance to ground of the crystal to device pcb trace c xoutpcb = the effective capacitance to ground of the crystal to device pcb trace c xindisc = any discrete capacitance that is placed between the xin pin and ground c xoutdisc = any discrete capacitance that is placed between the xout pin and ground c xinpcb c xoutpcb c xoutdisc c xindisc c xinftg c xoutftg xin xout clock generator as an example, and using this formula for this datasheet?s device, a design that has no discrete loading capacitors (c disc ) and each of the crystal to device pcb traces has a capacitance (c pcb ) to ground of 2pf (typical value) would calculate as: c l = (2pf + 30pf + 0pf) x (2pf + 30pf + 0pf) = 32 x 32 = 16 pf (2pf + 30pf + 0pf) + (2pf + 30pf + 0pf) 32 + 32 therefore to obtain output frequencies that are as close to this data sheets specified values as possible, in this design example, you should specify a parallel cut crystal, with c l = 16pf. pc133 clock generator for sis630/pentium ? iii & sis540/socket7 applications cypress semiconductor corporation 3901 north first st. document #: 38-07035 rev. *a 12/18/2002 san jose, ca 95134. tel: 408-943-2600 page 17 of 18 http://www.cypress.com a pproved produc t c9630 package drawing and dimensions 48 pin ssop outline dimensions inches millimeters symbol min nom max min nom max a 0.095 0.102 0.110 2.41 2.59 2.79 a 1 0.008 0.012 0.016 0.203 0.305 0.406 a2 0.088 - 0.092 2.24 - 2.34 b 0.008 - 0.0135 0.203 - 0.343 c 0.005 - 0.010 0.127 - 0.254 d 0.620 0.625 0.630 15.75 15.88 16.00 e 0.291 0.295 0.299 7.39 7.49 7.60 e 0.025 bsc 0.635 bsc h 0.395 - 0.420 10.03 - 10.67 l 0.020 - 0.040 0.508 - 1.016 a 0o - 8o 0o - 8o ordering information part number package type production flow c9630cy 48 pin ssop commercial, 0 to 70 c marking: example: cypress c9630cy date code, lot # c9630cy package y = ssop revision device number notice cypress semiconductor corporation reserves the right to make changes to its products in order to improve design, performance or reliability. cypress semiconductor corporation assumes no responsibility for the use of its products in life supporting and medical applications where the failure or malfunction of the product could cause failure of the life supporting and medical systems. products are not authorized for use in such applications unless a written approval is requested by the manufacturer and an approval is given in writing by cypress semiconductor corporation for the use of its products in the life supporting and medical applications. b e a a 1 a 2 e a l c d h pc133 clock generator for sis630/pentium ? iii & sis540/socket7 applications cypress semiconductor corporation 3901 north first st. document #: 38-07035 rev. *a 12/18/2002 san jose, ca 95134. tel: 408-943-2600 page 18 of 18 http://www.cypress.com a pproved produc t c9630 document title: c9630 pc133 clock generator for sis630/pentium?iii & sis540/socket7 applications document number: 38-07035 rev. ecn no. issue date orig. of change description of change ** 106963 06/11/01 ika convert from imi to cypress *a 122728 12/18/02 rbi added power-up requirements to maximum ratings information. |
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